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82541 Family of Gigabit Ethernet Controllers
82541PI, 82541GI, and 82541EI Networking Silicon
Datasheet
Revision 3.1 March 2004
Revision History
Date Mar 2004 Revision 3.1 Notes Included minor information for oscillator support in Section 3.5.1, "Crystal Signals." Revised regulator support in Table 4, "1.8V Supply Voltage Ramp" and Table 5, "1.8V Supply Voltage Ramp." Updated power specifications in Table 10, "Power Specifications - Complete Subsystem." Corrected minor typing errors throughout the document. Information for the 82541PI was added to the datasheet. Non-classified release.
Jan 2004 Aug 2003
3.0 2.0
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82541PI/GI/EI Gigabit Ethernet Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) 2004, Intel Corporation *Third-party brands and names are the property of their respective owners.
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Datasheet
82541 Family of Gigabit Ethernet Controllers
Contents
1.0 Introduction ...................................................................................................................... 1 1.1 1.2 1.3 2.0 Document Scope................................................................................................... 1 Reference Documents........................................................................................... 2 Block Diagram ....................................................................................................... 3
Features of the 82541 Family of Gigabit Ethernet Controllers..................................... 5 2.1 2.2 2.3 2.4 2.5 2.6 2.7 PCI Features ......................................................................................................... 5 MAC Specific Features.......................................................................................... 5 PHY Specific Features .......................................................................................... 6 Host Offloading Features ...................................................................................... 6 Manageability Features ......................................................................................... 7 Additional Device Features ................................................................................... 7 Technology Features............................................................................................. 8
3.0
Signal Descriptions.......................................................................................................... 9 3.1 3.2 Signal Type Definitions.......................................................................................... 9 PCI Bus Interface Signals (56) .............................................................................. 9 3.2.1 PCI Address, Data and Control Signals (44).......................................... 10 3.2.2 Arbitration Signals (2)............................................................................. 11 3.2.3 Interrupt Signal (1).................................................................................. 11 3.2.4 System Signals (4) ................................................................................. 11 3.2.5 Error Reporting Signals (2)..................................................................... 12 3.2.6 Power Management Signals (3) ............................................................. 12 3.2.7 SMB Signals (3) ..................................................................................... 12 EEPROM and Serial FLASH Interface Signals (9).............................................. 13 Miscellaneous Signals......................................................................................... 13 3.4.1 LED Signals (4) ...................................................................................... 13 3.4.2 Other Signals (4) .................................................................................... 14 PHY Signals ........................................................................................................ 14 3.5.1 Crystal Signals (2) .................................................................................. 14 3.5.2 Analog Signals (10) ................................................................................ 14 Test Interface Signals (6) .................................................................................... 15 Power Supply Connections ................................................................................. 15 3.7.1 Digital and Analog Supplies ................................................................... 15 3.7.2 Grounds, Reserved Pins and No Connects ........................................... 16 3.7.3 Voltage Regulation Control Signals (2) .................................................. 16
3.3 3.4
3.5
3.6 3.7
4.0
Voltage, Temperature, and Timing Specifications ...................................................... 17 4.1 4.2 Absolute Maximum Ratings................................................................................. 17 Targeted Recommended Operating Conditions.................................................. 17 4.2.1 General Operating Conditions................................................................ 17 4.2.2 Voltage Ramp and Sequencing Recommendations............................... 18 DC Specifications ................................................................................................ 19 AC Characteristics............................................................................................... 22 Timing Specifications .......................................................................................... 24
4.3 4.4 4.5
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82541 Family of Gigabit Ethernet Controllers
4.5.1 4.5.2 4.5.3 5.0
PCI Bus Interface ................................................................................... 24 Link Interface Timing .............................................................................. 28 EEPROM Interface................................................................................. 29
Package and Pinout Information .................................................................................. 31 5.1 5.2 5.3 5.4 Package Information ........................................................................................... 31 Thermal Specifications........................................................................................ 33 Pinout Information ............................................................................................... 34 Visual Pin Assignments....................................................................................... 44
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Datasheet
82541 Family of Gigabit Ethernet Controllers
1.0
Introduction
The Intel(R) 82541PI/GI/EI Gigabit Ethernet is a single, compact component with an integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop, workstation and mobile PC Network designs with critical space constraints, the Intel(R) 82541PI/GI/ EI allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10/100 Mbps Fast Ethernet designs. The Intel(R) 82541PI/GI/EI integrates fourth generation gigabit MAC design with fully integrated, physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral Component Interconnect (PCI) 2.3 compliant interface capable of operating at 33 or 66 MHz. The 82541PI/GI/EI also incorporates the CLKRUN protocol and hardware supported downshift capability to two-pair and three-pair 100 Mbps operation. These features optimize mobile applications. The 82541PI/GI/EI on-board System Management Bus (SMB) port enables network manageability implementations required by information technology personnel for remote control and alerting via the Local Area Network (LAN). With SMB, management packets can be routed to or from a management processor. The SMB port enables industry standards, such as Intelligent Platform Management Interface (IPMI) and Alert Standard Forum (ASF) 2.0, to be implemented using the 82541PI/GI/EI. In addition, on chip ASF 2.0 circuitry provides alerting and remote control capabilities with standardized interfaces. The 82541PI/GI/EI Gigabit Ethernet Controller Architecture is designed for high performance and low memory latency. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. The 82541PI/GI/EI controller includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface that maximizes efficient bus usage. The 82541PI/GI/EI uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached on chip. A large 64-KByte onchip packet buffer maintains superior performance as available PCI bandwidth changes. In addition, using hardware acceleration, the controller offloads tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP segmentation. The 82541PI/GI/EI is packaged in a 15 mm x 15 mm 196-ball grid array and is pin compatible with the 82551QM 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller, 82562EZ/ 82562EX Platform LAN Connect devices, the 82540EM Gigabit Ethernet Controller and the 82540EP Gigabit Ethernet Controller.
1.1
Document Scope
The 82541EI is the original device and is now being manufactured in a B-0 stepping. The 82541GI (B-1 stepping) and 82541PI (C-0 stepping) are pin compatible, however, a different Intel software driver is required from the 82541EI. This document contains datasheet specifications for the 82541PI/GI/EI Gigabit Ethernet Controllers including signal descriptions, DC and AC parameters, packaging data, and pinout information.
Datasheet
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82541 Family of Gigabit Ethernet Controllers
1.2
Reference Documents
This document assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information:
* 82540EP/82541EI & 825462EZ(EX) Dual Footprint Design Guide, AP-444. Intel
Corporation.
* 82547GI(EI)/82541GI(EI)/82541ER EEPROM Map and Programming Information Guide,
AP-446. Intel Corporation.
* PCI Local Bus Specification, Revision 2.3. PCI Special Interest Group (SIG). * PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest Group
(SIG).
* IEEE Standard 802.3, 2000 Edition. Incorporates various IEEE standards previously published
separately. Institute of Electrical and Electronic Engineers (IEEE).
* 82559 Fast Ethernet Controllers Timing Device Selection Guide, AP-419. Intel Corporation. * PCI Mobile Design Guide, Revision 1.1. PCI Special Interest Group (SIG).
Software driver developers should contact their local Intel representatives for programming information.
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Datasheet
82541 Family of Gigabit Ethernet Controllers
1.3
Block Diagram
PCI Core EEPROM FLASH
Slave Access Logic
DMA Function Descriptor Management 64KB Packet RAM
Control Status Logic
TX/RX MAC CSMA/CD VLA N
RX Filters (Perfect, VLAN)
Statistics
8 bits 8 bits
Management Interface Side-stream Scrambler/ Descrambler
Trellis Viterbi Encoder/Decoder
4 bits 4 bits
PHY Control
ECHO, NEXT, FEXT Cancellers AGC, A/D Timing Recovery
4DPAM5 Encoder
Pulse Shaper, DAC, Filter
Hybrid
Line Driver
Media Dependent Interface
Figure 1. 82541PI/GI/EI Block Diagram
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82541 Family of Gigabit Ethernet Controllers
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Datasheet
82541 Family of Gigabit Ethernet Controllers
2.0
Features of the 82541 Family of Gigabit Ethernet Controllers
PCI Features
Features * PCI Revision 2.3 support for 32-bit wide interface at 33 MHz and 66 MHz * * Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands CLKRUN# Signal 3.3 V (5 V tolerant) PCI signaling. * * * Benefits Application flexibility for LAN on Motherboard (LOM) or embedded solutions 64-bit addressing for systems with more than 4 Gigabytes of physical memory Support for new PCI 2.3 interrupt status/control Efficient bus operations PCI clock suspension for low power mobile design Flexible system design
2.1
2.2
MAC Specific Features
Features Low-latency transmit and receive queues IEEE 802.3x compliant flow control support with software controllable pause times and threshold values Caches up to 64 packet descriptors in a single burst Programmable host memory receive buffers (256 Bytes to 16 KBytes) and cache line size (16 Bytes to 256 Bytes) Wide, optimized internal data path architecture 64 KByte configurable Transmit and Receive FIFO buffers (default is 16 KB of transmit FIFO space and 24 KB of receive FIFO space). Descriptor ring management hardware for transmit and receive Optimized descriptor fetching and write-back mechanisms Mechanism available for reducing interrupts generated by transmit and receive operations Support for transmission and reception of packets up to 16 KBytes * * * * * * * * * * Benefits Network packets handled without waiting or buffer overflow Control over the transmission of pause frames through software or hardware triggering Frame loss reduced from receive overruns Efficient use of PCI bandwidth Efficient use of PCI bandwidth Low latency data handling Superior DMA transfer rate performance No external FIFO memory requirements FIFO size adjustable to application Simple software programming model Efficient system memory and use of PCI bandwidth Maximizes system performance and throughput Enables jumbo frames
* *
Datasheet
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82541 Family of Gigabit Ethernet Controllers
2.3
PHY Specific Features
Features * Integrated PHY for 10/100/1000 Mbps operation * * * * * * * Benefits Smaller footprint and lower power dissipation compared to other multi-chip MAC and PHY solutions Automatic link configuration including speed, duplex, and flow control Robust operation over the installed base of Category-5 (CAT-5) twisted pair cabling Robust performance in noisy environments Tolerance of common electrical signal impairments Easier network installation and maintenance End-to-end wiring tolerance Assures link under adverse cable configurations
IEEE 802.3ab Auto-Negotiation support IEEE 802.3ab PHY compliance and compatibility State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and crosstalk cancellation Automatic polarity detection Automatic detection of cable lengths and MDI versus MDI-X cable at all speeds Two-pair and three-pair cable downshift
2.4
Host Offloading Features
Features Transmit and receive IP, TCP, and UDP checksum offloading capabilities Transmit TCP segmentation * * * * Advanced packet filtering * * IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags Descriptor ring management hardware for transmit and receive 16 KByte jumbo frame support (9KB jumbo frame also supported) Intelligent interrupt generation (multiple packets per interrupt) * * Benefits Lower CPU utilization Increased throughput and lower CPU utilization Large send offload feature (in Microsoft* Windows* XP) compatible 16 exact matched packets (unicast or multicast) 4096-bit hash filter for multicast frames Promiscuous (unicast and multicast) transfer mode support Optional filtering of invalid frames Ability to create multiple virtual LAN segments Optimized fetching and write-back mechanisms for efficient system memory and PCI bandwidth usage High throughput for large data transfers on networks supporting jumbo frames Increased throughput by reducing interrupts generated by transmit and receive operations
* *
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Datasheet
82541 Family of Gigabit Ethernet Controllers
2.5
Manageability Features
Features Manageability features: * * * * SMB port Alerting Standards Format 1.0 and 2.0 Advanced Power Management (Wake on LAN) Advanced Configuration and Power Interface (ACPI) * On-board SMB port Compliance with PCI Power Management 1.1 and ACPI 2.0 register set compliant including: * * * D0 and D3 power states Network Device Class Power Management Specification 1.1 PCI Specification 2.3 * * * Easy system monitoring with industry standard consoles Remote network management capabilities through DMI 2.0 and SNMP software Packet recognition and wake-up for NIC and LOM applications without software configuration * PCI power management capability requirements for PC and embedded applications * Enables IPMI and ASF implementations Allows packets routing to and from either LAN port and a server management processor * Network management flexibility Benefits
SNMP and RMON statistic counters SDG 3.0, WfM 2.0, and PC2001 compliance Wake on LAN support
2.6
Additional Device Features
Features Four activity and link indication outputs that directly drive LEDs Programmable LED functionality * * * Benefits Link and activity indications (10, 100, and 1000 Mbps) Software definable function (speed, link, and activity) and blinking allowing flexible LED implementations Allows LAN Port enabling/disabling through BIOS control (OS not needed) Lower component count and system cost Simplified testing using boundary scan Reduced number of on-board power supply regulators Simplified power supply design in less powercritical applications Additional flexibility for LEDs or other low speed I/O devices Portable across application architectures Validates silicon integrity
Single-pin LAN Disable Function Internal PLL for clock generation can use a 25 MHz crystal JTAG (IEEE 1149.1) Test Access Port built in silicon
* * *
On-chip power control circuitry
* *
Four software definable pins Supports both little and big endian byte ordering for both 32 and 64 bit systems Provides loopback capabilities
* *
Datasheet
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82541 Family of Gigabit Ethernet Controllers
2.7
Technology Features
Features * 196-pin Ball Grid Array (BGA) package * Benefits 15 mm x 15 mm component occupies same board space as earlier products capable up to 10/100 Mbps operation. Enables 10/100 Mbps Fast Ethernet or 1000 Mbps Gigabit Ethernet implementations on the same board with only minor stuffing option changes Offers lowest geometry to minimize power and size while maintaining Intel quality reliability standards Simple thermal design
Pin compatible with 82551QM, 82540EM and 82540EP controllers
* Implemented in 0.13 CMOS process 0 C to 70 C (maximum) operating ambient temperature Heat sink or forced airflow not required Typical targeted silicon power dissipation: * * * 1.1 W @ D0 1000 Mbps 300 mW@ D3 100 Mbps (wake up enabled) 25 mW @ D3 wakeup disabled *
*
Minimize impact of power requirements for mobile, desktop and workstation applications
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Datasheet
82541 Family of Gigabit Ethernet Controllers
3.0
3.1
Signal Descriptions
Signal Type Definitions
The signals of the 82541PI/GI/EI controller are electrically defined as follows:
Name I O TS Input. Standard input only digital signal. Output. Standard output only digital signal. Tri-state. Bi-directional tri-state digital input/output signal. Sustained Tri-state. An active low tri-state signal owned and driven by only one agent at a time. The agent that drives an STS pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving an STS signal any sooner than one clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. Open Drain. Wired-OR with other agents. OD The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the de-asserted state. Analog. PHY analog data signal. Power. Power connection, voltage reference, or other reference connection. Definition
STS
A P
3.2
PCI Bus Interface Signals (56)
When the Reset signal (RST#) is asserted, the 82541PI/GI/EI will not drive any PCI output or bidirectional pins. The Power Management Event signal (PME#) can be active by configuring manageability functions.
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82541 Family of Gigabit Ethernet Controllers
3.2.1
PCI Address, Data and Control Signals (44)
Symbol Type Name and Function Address and Data. Address and data signals are multiplexed on the same PCI pins. A bus transaction includes an address phase followed by one or more data phases. AD[31:0] TS The address phase is the clock cycle when the Frame signal (FRAME#) is asserted low. During the address phase AD[31:0] contain a physical address (32 bits). For I/O, this is a byte address, and for configuration and memory, a DWORD address. The 82541PI/GI/EI device uses little endian byte ordering. During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24] contain the most significant byte (MSB). Bus Command and Byte Enables. Bus command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, CBE[3:0]# define the bus command. In the data phase, CBE[3:0]# are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data. CBE0# applies to byte 0 (LSB) and CBE3# applies to byte 3 (MSB). Parity. The Parity signal is issued to implement even parity across AD[31:0] and CBE[3:0]#. PAR is stable and valid one clock after the address phase. During data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted after a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. When the 82541PI/GI/EI controller is a bus master, it drives PAR for address and write data phases, and as a slave device, drives PAR for read data phases. Cycle Frame. The Frame signal is driven by the 82541PI/GI/EI device to indicate the beginning and length of a bus transaction. While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the transaction is in the final data phase. Initiator Ready. Initiator Ready indicates the ability of the 82541PI/GI/EI controller (as a bus master device) to complete the current data phase of the transaction. IRDY# is used in conjunction with the Target Ready signal (TRDY#). The data phase is completed on any clock when both IRDY# and TRDY# are asserted. During the write cycle, IRDY# indicates that valid data is present on AD[31:0]. For a read cycle, it indicates the master is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82541PI/GI/EI controller drives IRDY# when acting as a master and samples it when acting as a slave. Target Ready. The Target Ready signal indicates the ability of the 82541PI/GI/EI controller (as a selected device) to complete the current data phase of the transaction. TRDY# is used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed on any clock when both TRDY# and IRDY# are sampled asserted. During a read cycle, TRDY# indicates that valid data is present on AD[31:0]. For a write cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82541PI/GI/EI device drives TRDY# when acting as a slave and samples it when acting as a master. Stop. The Stop signal indicates the current target is requesting the master to stop the current transaction. As a slave, the 82541PI/GI/EI controller drives STOP# to request the bus master to stop the transaction. As a master, the 82541PI/GI/EI controller receives STOP# from the slave to stop the current transaction.
CBE[3:0]#
TS
PAR
TS
FRAME#
STS
IRDY#
STS
TRDY#
STS
STOP#
STS
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Datasheet
82541 Family of Gigabit Ethernet Controllers
Symbol IDSEL#
Type I
Name and Function Initialization Device Select. The Initialization Device Select signal is used by the 82541PI/GI/EI as a chip select signal during configuration read and write transactions. Device Select. When the Device Select signal is actively driven by the 82541PI/GI/EI, it signals notifies the bus master that it has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI signaling environment). It is used as the clamping voltage. Note: VIO should be connected to 3.3V Aux or 5V Aux in order to be compatible with the PullUp clamps spec.
DEVSEL#
STS
VIO
P
3.2.2
Arbitration Signals (2)
Symbol REQ# GNT# Type TS I Name and Function Request Bus. The Request Bus signal is used to request control of the bus from the arbiter. This signal is point-to-point. Grant Bus. The Grant Bus signal notifies the 82541PI/GI/EI that bus access has been granted. This is a point-to-point signal.
3.2.3
Interrupt Signal (1)
Symbol INTA# Type TS Name and Function Interrupt A. Interrupt A is used to request an interrupt of the 82541PI/GI/EI. It is an active low, level-triggered interrupt signal.
3.2.4
System Signals (4)
Symbol Type Name and Function PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus and is an input to the 82541PI/GI/EI device. All other PCI signals, except the Interrupt A (INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other timing parameters are defined with respect to this edge. 66 MHz Enable. M66EN indicates whether the system bus is enabled for 66MHz PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the Power Management Event signal (PME#), are floated and all input signals are ignored. The PME# context is preserved, depending on power management settings. Most of the internal state of the 82541PI/GI/EI is reset on the de-assertion (rising edge) of RST#. CLKRUN# I/O OD Clock Run.. This signal is used by the system to pause the PCI clock signal. It is used by the 82541PI/GI/EI controller to request the PCI clock. When the CLKRUN# feature is disabled, leave this pin unconnected.
CLK
I
M66EN
I
RST#
I
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82541 Family of Gigabit Ethernet Controllers
3.2.5
Error Reporting Signals (2)
Symbol SERR# Type OD Name and Function System Error. The System Error signal is used by the 82541PI/GI/EI controller to report address parity errors. SERR# is open drain and is actively driven for a single PCI clock when reporting the error. Parity Error. The Parity Error signal is used by the 82541PI/GI/EI controller to report data parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained tri-state and must be driven active by the 82541PI/GI/EI controller two data clocks after a data parity error is detected. The minimum duration of PERR# is one clock for each data phase a data parity error is present.
PERR#
STS
3.2.6
Power Management Signals (3)
Symbol LAN_ PWRGD Type I Name and Function Power Good (Power-on Reset). The Power Good signal is used to indicate that stable power is available for the 82541PI/GI/EI. When the signal is low, the 82541PI/GI/EI holds itself in reset state and floats all PCI signals. Power Management Event. The 82541PI/GI/EI device drives this signal low when it receives a wake-up event and either the PME Enable bit in the Power Management Control/Status Register or the Advanced Power Management Enable (APME) bit of the Wake-up Control Register (WUC) is 1b. Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available and the 82541PI/GI/EI device should support the D3cold power state.
PME#
OD
AUXPWR
I
3.2.7
SMB Signals (3)
Symbol SMBCLK SMBDATA SMBALRT# /PCI_PWR GOOD Type TS OD TS OD TS OD Name and Function SMB Clock. The SMB Clock signal is an open drain signal for serial SMB interface. SMB Data. The SMB Data signal is an open drain signal for serial SMB interface. Multiplexed pin: SMB Alert, PWRGOOD. The SMB Alert signal is open drain for serial SMB interface. The signal acts as an interrupt pin of a slave device on the SMBUS in TCO mode. (82559 mode). In ASF mode, this signal acts as PWRGOOD input.
Note:
If the SMB is disconnected, then an external pullup should be used for these pins.
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Datasheet
82541 Family of Gigabit Ethernet Controllers
3.3
EEPROM and Serial FLASH Interface Signals (9)
Symbol Type Name and Function EEPROM Mode. The EEPROM Mode pin is used to select the interface and source of the EEPROM used to initialize the device. For a MIcrowire* EEPROM on the standard EEPROM pins, tie this pin to ground with a 1 K pull-down resistor (for the 82541PI, use a 100 pull-down resistor instead). For an Serial Peripheral Interface (SPI*) EEPROM attached to the Flash memory pins, leave this pin unconnected. EEPROM Data Input. The EEPROM Data Input pin is used for output to the memory device. EEPROM Data Output. The EEPROM Data Output pin is used for input from the memory device. The EE_DO includes an internal pull-up resistor. EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device. EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the EEPROM interface, which is approximately 1 MHz for Microwire* and 2MHZ for SPI. FLASH Chip Enable Output. Used to enable FLASH device. FLASH Serial Clock Output. The clock rate of the serial FLASH interface is approximately 1 MHz. FLASH Serial Data Input. This pin is an output to the memory device. FLASH Serial Data Output / LAN Disable. This pin is an input from the FLASH memory. Alternatively, the pin can be used to disable the LAN port from a system GP (General Purpose) port. It has an internal pullup device. If the 82541PI/GI/EI is not using Flash functionality, the pin should be connected to external pull-up resistor. If this pin is used as LAN_DISABLE#, the device goes to low power state and the LAN port is disabled when the pin is sampled low on rising edge of PCI reset.
EE_MODE
I
EE_DI EE_DO EE_CS
O I O
EE_SK FLSH_CE# FLSH_SCK FLSH_SI
O O O O
FLSH_SO/ LAN_DISABLE#
I
3.4
3.4.1
Miscellaneous Signals
LED Signals (4)
Symbol LED0 / LINKUP# LED1 / ACT# LED2 / LINK100# LED3 / LINK1000# Type O O O O Name and Function LED0 / LINK Up. Programmable LED indication. Defaults to indicate link connectivity. LED1 / Activity. Programmable LED indication. Defaults to flash to indicate transmit or receive activity. LED2 / LINK 100. Programmable LED indication. Defaults to indicate link at 100 Mbps. LED3 / LINK 1000. Programmable LED indication. Defaults to indicate link at 1000 Mbps.
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82541 Family of Gigabit Ethernet Controllers
3.4.2
Other Signals (4)
Symbol Type Name and Function Software Defined Pin. The Software Defined Pins are reserved and programmable with respect to input and output capability. These default to input signals upon power-up but may be configured differently by the EEPROM. The upper two bits may be mapped to the General Purpose Interrupt bits if they are configured as input signals.
SDP[3:0]
TS
3.5
3.5.1
PHY Signals
Crystal Signals (2)
Symbol XTAL1 XTAL2
Type I O
Name and Function Crystal One. The Crystal One pin is a 25 MHz +/- 30 ppm input signal. It should be connected to a crystal, and the other end of the crystal should be connected to XTAL2. Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation.
Note:
The 82541 clock input circuit is optimized for use with an external crystal. However, an oscillator may also be used in place of the crystal with the proper design considerations. The 82540EP/82541 Family & 82562EZ(EX) Dual Footprint Design Guide (AP-444) should be consulted for further details.
3.5.2
Analog Signals (10)
Symbol Type Name and Function Media Dependent Interface [0]. 1000BASE-T: In MDI configuration, MDI[0]+/- corresponds to BI_DA+/-, and in MDI-X configuration, MDI[0]+/- corresponds to BI_DB+/-. MDI[0]+/A 100BASE_TX: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair. 10BASE-T: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair. Media Dependent Interface [1]. 1000BASE-T: In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-, and in MDI-X configuration, MDI[1]+/- corresponds to BI_DA+/-. MDI[1]+/A 100BASE_TX: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair. 10BASE-T: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair. Media Dependent Interface [2]. MDI[2]+/A 1000BASE-T: In MDI configuration, MDI[2]+/- corresponds to BI_DC+/-, and in MDIX configuration, MDI[2]+/- corresponds to BI_DD+/-. 100BASE_TX: Unused. 10BASE-T: Unused.
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Datasheet
82541 Family of Gigabit Ethernet Controllers
Media Dependent Interface [3]. MDI[3]+/A 1000BASE-T: In MDI configuration, MDI[3]+/- corresponds to BI_DC+/-, and in MDIX configuration, MDI[3]+/- corresponds to BI_DD+/-. 100BASE_TX: Unused. 10BASE-T: Unused. IEEE_TESTIEEE_TEST+ A A IEEE test pin output minus. Used to gain access to the internal PHY clock for 1000BASE-T IEEE physical layer conformance testing. Analog test pin output plus. Used to gain access to the internal PHY clock for 1000BASE-T IEEE physical layer conformance testing.
3.6
Test Interface Signals (6)
Symbol TEST JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS Type I I I O I Name and Function Test Enable. Enables test mode. Normal mode: connect to VSS. JTAG Test Access Port Clock. JTAG Test Access Port Data In. JTAG Test Access Port Data Out. JTAG Test Access Port Mode Select. JTAG Test Access Port Reset. This is an active low reset signal for JTAG. To disable the JTAG interface, this signal should be terminated using pulldown resistor (1 K for the 82541EI(GI) and 100 for the 82541PI) to ground. It must not be left unconnected.
JTAG_TRST#
I
3.7
3.7.1
Power Supply Connections
Digital and Analog Supplies
Symbol 3.3V Analog_1.8V CLKR_1.8V XTAL_1.8V 1.2V Analog_1.2V PLL_1.2V
Type P P P P P P P 3.3V I/O Power Supply. 1.8V Analog Power Supply.
Name and Function
1.8V analog power supply for the clock recovery. Input power for the XTAL regulator. 1.2V Power supply. For analog and digital circuits. 1.2V Analog Power Supply. Input power for the ICS regulator.
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82541 Family of Gigabit Ethernet Controllers
3.7.2
Grounds, Reserved Pins and No Connects
Symbol VSS AVSS RSVD_VSS Type P P P Ground. Shared analog Ground. Reserved Ground. This pin is reserved by Intel and may have factory test functions. For normal operation, connect to ground. Reserved No connect. This pin is reserved by Intel and may have factory test functions. For normal operation, do not connect any circuit to these pins. Do not connect pull-up or pull-down resistors. No Connect. This pin is not connected internally. Name and Function
RSVD_NC NC
P P
3.7.3
Voltage Regulation Control Signals (2)
Symbol Type Name and Function 1.2V Control. LDO voltage regulator output to drive external PNP pass transistor. If 1.2V is already present in the system, leave output unconnected. To achieve optimal D3 power consumption, leave the output unconnected and use a high-efficiency external regulator. 1.8V Control. LDO voltage regulator output to drive external PNP pass transistor. If 1.8V is already present in the system, leave output unconnected. To achieve optimal D3 power consumption, leave the output unconnected and use a high-efficiency external regulator.
CTRL_12
A
CTRL_18
A
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Datasheet
82541 Family of Gigabit Ethernet Controllers
4.0
4.1
Table 1.
Voltage, Temperature, and Timing Specifications
Absolute Maximum Ratings
Absolute Maximum Ratingsa
Symbol VDD (3.3) VDD (1.8) VDD (1.2) VDD VI / VO IO TSTG Parameter DC supply voltage on 3.3 V pins with respect to VSS DC supply voltage on 1.8 V pins with respect to VSS DC supply voltage on 1.2 V pins with respect to VSS DC supply voltage Input voltage Output current Storage temperature range ESD per MIL_STD-883 Test Method 3015, Specification 2001V Latchup Over/Undershoot: 150 mA, 125 C -40 Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 Max 4.6 2.5 or VDD(1.8) + 0.5b 1.7 or VDD(1.2) + 0.5c 4.6 4.6d 40 125 VDD overstress: VDD(3.3) * (7.2 V) Unit V V V V V mA C
V
a. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are exceeded. These values should not be used as the limits for normal device operations. b. The maximum value is the lesser value of 2.5 V or VDD(2.5) + 0.5 V. This specification applies to biasing the device to a steady state for an indefinite duration. c. The maximum value is the lesser value of 1.7 V or VDD(2.5) + 0.5 V. d. The maximum value must also be less than VIO.
4.2
4.2.1
Table 2.
Targeted Recommended Operating Conditions
General Operating Conditions
Recommended Operating Conditions (Sheet 1 of 2)a
Symbol VDD (3.3) VDD (1.8) VDD (1.2) VIO tR / tF Parameter DC supply voltage on 3.3 V pins DC supply voltage on 1.8 V pins DC supply voltage on 1.2 V pins PCI bus reference voltage Input rise/fall time (normal input)
b
Min 3.0 1.71
c
Max 3.6 1.89 1.26 5.25 200
Unit V V V V ns
1.14d 3.0 0
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82541 Family of Gigabit Ethernet Controllers
Table 2.
Recommended Operating Conditions (Sheet 2 of 2)a
Symbol tr/tf TA TJ Parameter input rise/fall time (Schmitt input) Operating temperature range (ambient) Junction temperature Min 0 0 Max 10 70 125 Unit ms C C
a. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating limits, might result in permanent damage. b. It is recommended for 3.3 V pins to be of a value greater than 1.8 V pins, with a value greater than 1.2 V pins, during powerup (3.3 V pins > 1.8 V pins > 1.2 V pins). However, voltage sequencing is not a strict requirement if the power supply ramp is faster than approximately 20 ms. c. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1.67 V. d. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1.12 V.
4.2.2
Table 3.
Voltage Ramp and Sequencing Recommendations
3.3V Supply Voltage Ramp
Parameter Rise Time Monotonicity Slope Operational Range Ripple Overshoot Description Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Maximum voltage ripple at a bandwith equal to 50 MHz Maximum voltage allowed 3 Min 0.1 Max 100a 0 28800 3.6 70 4 Unit ms mV V/s V mV V
a. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
Table 4.
1.8V Supply Voltage Ramp
Symbol Rise Time Monotonicity Slope Operational Range Ripple Ripple Overshoot Output Capacitance Parameter Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Maximum voltage ripple at frequency below 1 MHz Minimum voltage ripple at frequency below 1 MHz Maximum voltage allowed Capacitance range when using PNP circuit 4.7 1.55 2.2 20 1.71 Min 0.1 Max 100 0 57600 1.89 280
a
Unit ms mV V/s V mVpk-to-pk V V F
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Datasheet
82541 Family of Gigabit Ethernet Controllers
Table 4.
1.8V Supply Voltage Ramp
Input Capacitance Capacitance ESR Ictrl_18 Capacitance range when using PNP circuit Equivalent series resistance of output capacitanceb Maximum output current rating to CTRL_18 4.7 5 20 100 20 F m mA
a. Good design practices achieve voltage ramps to within the regulation bands in approximately 20ms or less. b. Tantalum capacitors must not be used.
Table 5.
1.2V Supply Voltage Ramp
Symbol Rise Time Monotonicity Slope Operational Range Ripple Ripple Overshoot Output Capacitance Input Capacitance Capacitance ESR Ictrl_12 Parameter Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Maximum voltage ripple at frequency below 1 MHz Maximum voltage ripple at frequency below 1 MHz Maximum voltage allowed Capacitance range when using PNP circuit Capacitance range when using PNP circuit Equivalent series resistance of output capacitancea Maximum output current rating to CTRL_12 4.7 4.7 5 1 1.45 20 20 100 20 1.14 Min 0.025 0 38400 1.26 180 Max Unit ms mV V/s V mVpk-to-pk V V F F m mA
a. Tantalum capacitors must not be used.
Note:
In any case or time period (greater than 1 ns), the supply voltage should comply with 3.3V > 1.8V > 1.2V. This is important to avoid stress in the ESD protection circuits. After 3.3V reaches 10% of its final value, all voltage rails (1.8V and 1.2V) have 150 ms to reach their final operating values.
4.3
Table 6.
DC Specifications
DC Characteristics
Symbol VDD (3.3) VDD (1.8) VDD (1.2) Parameter DC supply voltage on 3.3 V pins DC supply voltage on 1.8 V pins DC supply voltage on 1.2 V pins Condition Min 3.00 1.71a 1.14b Typ 3.3 1.8 1.2 Max 3.60 1.89 1.26 Units V V V
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19
82541 Family of Gigabit Ethernet Controllers
a. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1.67 V. b. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1.12 V.
Table 7.
Power Specifications - D0a
D0a unplugged no link Typ Icc (mA)a 3.3V 1.8V 1.2V Total Device Power 3 mA 14 mA 30 mA Max Icc (mA)b 5 mA 15 mA 35 mA @10 Mbps Typ Icc (mA)a 5 mA 85 mA 85 mA Max Icc (mA)b 10 mA 85 mA 90 mA @100 Mbps Typ Icc (mA)a 13 mA 110 mA 90 mA Max Icc (mA)b 15 mA 115 mA 100 mA @ 1000 Mbps Typ Icc (mA)a 30 mA 315 mA 380 mA Max Icc (mA)b 40 mA 320 mA 400 mA
75 mW
85 mW
270 mW
295 mW
350 mW
380 mW
1.1 W
1.2 W
a. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz system interface. b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI 33 MHz system interface.
Table 8.
Power Specifications - D3cold
D3cold - wake-up enableda D3cold-wake disabled unplugged link Typ Icc (mA)b 3.3V 1.8V 1.2V Total Device Power 2 mA 14 mA 21 mA Max Icc (mA)c 3 mA 15 mA 25 mA @10 Mbps Typ Icc (mA)a 2 mA 20 mA 30 mA Max Icc (mA)b 3 mA 25 mA 35 mA @100 Mbps Typ Icc (mA)a 2 mA 110 mA 80 mA Max Icc (mA)b 3 mA 115 mA 85 mA Typ Icc (mA)a 4 mA 1 mA 7 mA Max Icc (mA)b 5 mA 2 mA 10 mA
60 mW
70 mW
80 mW
100 mW
300 mW
320 mW
25 mW
35 mW
a. At 1000 Mbps, power consumption is not shown since the controller switches to the 10/100 Mbps state before entering D3 to conserve power. b. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz system interface. c. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI 33 MHz system interface.
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82541 Family of Gigabit Ethernet Controllers
Table 9.
Power Specifications D(r) Uninitialized
D(r) Uninitialized (FLSH_SO/LAN_DISABLE# = 0) Typ Icc (mA) 3.3V 1.8V 1.2V Total Device Power 5 mA 1 mA 12 mA Max Icc (mA) 10 mA 2 mA 15 mA
35 mW
Table 10. Power Specifications - Complete Subsystem
Complete Subsystem (Reference Design) Including Magnetics, LED, Regulator Circuits D3cold wake disabled Typ Icc (mA)a 3.3 V 1.8 V 1.2 V Sub-system Power 4 1 7 40 mW Max Icc (mA)b 5 2 10 60 mW D3cold wakeenabled @ 10 Mbps Typ Icc (mA)a 2 20 30 175 mW Max Icc (mA)b 3 25 35 210 mW D3cold wakeup enabled @ 100 Mbps Typ Icc (mA)a 6 110 80 650 mW Max Icc (mA)b 7 115 85 685 mW D0 @10 Mbps active Typ Icc (mA)a 7 85 85 585 mW Max Icc (mA)b 12 85 90 620 mW D0 @100 Mbps active Typ Icc (mA)a 19 110 90 725 mW Max Icc (mA)b 21 115 100 780 mW D0 @ 1000 Mbps active Typ Icc (mA)a 36 315 380 2.4 W Max Icc (mA)b 46 320 400 2.5 W
a. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz system interface. b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI 33 MHz system interface.
Table 11. I/O Characteristics (Sheet 1 of 2)
Symbol Parameter Condition 3.3 V PCI VIH Input high voltage SMB Non-SMBa VIL Input low voltage SMB VSS 0.8 2.1 VSS VDD(3.3) or VIO 0.3 * VDD(3.3) V Min 0.5 * VDD(3.3) Typ Max VDD(3.3) or VIO V Units
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82541 Family of Gigabit Ethernet Controllers
Table 11. I/O Characteristics (Sheet 2 of 2) (Continued)
Symbol Parameter Input current Input with pulldown resistor (50 K) Inputs with pull-up resistor (50 K) Condition 0 < VIN < VDD(3.3) VIN = VDD(3.3) Min -10 28 Typ Max 10 191 A Units
IIN
VIN = VSS 3.3 V PCIb
-28
-191 2.09 100 * VOUT mA
IOL
Output low current
0 VOUT 3.6V 0 VOUT 1.3V 1.3V VOUT 3.6V 0 (VDD-VOUT) 3.6V 48 * VOUT 5.7 * VOUT+ 55
-74 * (VDD VOUT) -32 * (VDD VOUT) -11 * (VDD VOUT)-25.2 -1.8 * (VDD VOUT)-42.7 V
IOH
Output high current:
0 (VDD-VOUT) 1.2V 1.2V (VDD-VOUT) 1.9V 1.9V (VDD-VOUT) 3.6V
mA
VOH
Output high voltage: 3.3 V PCI IOH = -500 mA 0.9 * VDD(3.3)
VOL
Output low voltage: 3.3 V PCI IOL = 1500 mA VO = VDD or VSS -10 0.1 * VDD(3.3) 10 -250 Input and bidirectional buffers 8
V
IOZ IOS CIN
Off-state output leakage current Output short circuit current Input capacitancec
A
pF
a. This is only applicable to the 82541PI. The maximum VIL is 0.6 V for the following pins: A13, C5, C8, J4, L7, L13, L12, M8, M12, M13, N10, N11, N13, N14, P9, and P13. b. This is only applicable to the 82541PI. c. VDD (3.3) = 0 V; TA = 25 C; f = 1 Mhz
4.4
AC Characteristics
Table 12. AC Characteristics: 3.3 V Interfacing
Symbol PCICLK Parameter Clock frequency in PCI mode Min Typ Max 66 Unit MHz
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82541 Family of Gigabit Ethernet Controllers
Table 13. 25 MHz Clock Input Requirements
Specifications Symbol f0 df0 Dc tr tf Jptp Cin T Aptp Vcm Frequency Frequency variation Duty cycle Rise time Fall time Clock jitter (peak-to-peak) Input capacitance Operating temperature Input clock amplitude (peak-to-peak) Clock common mode 1.0 1.2 0.6
a
Parameter Min Typ 25 -50 40 +50 60 5 5 250 20 70 1.3 Max
Units MHz ppm % ns ns ps pF C V V
a. Clock jitter is defined according to the recommendations of part 40.6.1.2.5 IEEE 1000BASE-T Standard (at least 105 clock edges, filtered by HPF with cut off frequency 5000 Hz).
Table 14. Reference Crystal Specification Requirements
Specification Vibrational Mode Nominal Frequency Frequency Tolerance Temperature Stability Calibration Mode Load Capacitance Shunt Capacitance Series Resistance, Rs Drive Level Aging Insulation Resistance Fundamental 25.000 MHz at 25 C 30 ppm 30 ppm at 0 C to 70 C Parallel 20 pF to 24 pF 6 pF maximum 50 W maximum 0.5 mW maximum 5.0 ppm per year maximum 500 M at DC 100 V Value
Table 15. Link Interface Clock Requirements
Symbol fGTX
a
Parameter GTX_CLK frequency
Min
Typ 125
Max
Unit MHz
a. GTX_CLK is used externally for test purposes only.
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82541 Family of Gigabit Ethernet Controllers
Table 16. EEPROM Interface Clock Requirements
Symbol fSK SPI EEPROM Clock 2 MHz Parameter Microwire EEPROM Clock Min Typ Max 1 Unit MHz
Table 17. AC Test Loads for General Output Pins
Symbol CL CL CL CL TDO PME#, SDP[3:0] EE_DI, EE_SK LED[3:0] Signal Name Value 10 16 18 20 Units pF pF pF pF
CL
Figure 1. AC Test Loads for General Output Pins
4.5
4.5.1
4.5.1.1
Timing Specifications
PCI Bus Interface
PCI Bus Interface Clock
Table 18. PCI Bus Interface Clock Parameters
PCI 66 MHz Symbol TCYC TH TL Parametera Min CLK cycle time CLK high time CLK low time CLK slew rate RST# slew rateb 15 6 6 1.5 50 4 Max 30 Min 30 11 11 1 50 4 Max ns ns ns V/ns mV/ns PCI 33 MHz Units
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Datasheet
82541 Family of Gigabit Ethernet Controllers
a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown. b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot render a monotonic signal to appear bouncing in the switching range.
Tcyc
3.3 V Clock
Th 0.6 Vcc
0.4 Vcc p-to-p (minimum)
0.5 Vcc 0.4 Vcc 0.3 Vcc
0.2 Vcc Tl
Figure 1. PCI Timing Clock
4.5.1.2
PCI Bus Interface Timing
Table 19. PCI Bus Interface Timing Parameters
PCI 66MHz Symbol Parameter Min TVAL TVAL(ptp) TON TOFF TSU TSU(ptp) TH CLK to signal valid delay: bussed signals CLK to signal valid delay: pointto-point signals Float to active delay Active to float delay Input setup time to CLK: bussed signals Input setup time to CLK: point-topoint signals Input hold time from CLK 3 5 0 2 2 2 14 7 10, 12 0 Max 6 6 Min 2 2 2 28 Max 11 12 ns ns ns ns ns ns ns PCI 33 MHz Units
NOTES: 1. Output timing measurements are as shown. 2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed. 3. Input timing measurements are as shown.
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82541 Family of Gigabit Ethernet Controllers
VTH PCI_CLK VTEST VTL
Output Delay
output current leakage current
VTEST VSTEP (3.3V Signalling)
Tri-State Output TON TOFF
Figure 2. PCI Bus Interface Output Timing Measurement
VTH PCI_CLK VTEST VTL TSU VTH Input VTL VTEST Input Valid VTEST VMAX TH
Figure 3. PCI Bus Interface Input Timing Measurement Condition
Table 20. PCI Bus Interface Timing Measurement Conditions
Symbol VTH VTL VTEST Parameter Input measurement test voltage (high) Input measurement test voltage (low) Output measurement test voltage Input signal slew rate PCI 66 MHz 3.3 v 0.6 * VCC 0.2 * VCC 0.4 * VCC 1.5 Unit V V V V/ns
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Datasheet
82541 Family of Gigabit Ethernet Controllers
Pin 1/2 inch max.
Test Point
25 10 pF
Figure 4. TVAL (max) Rising Edge Test Load
Pin 1/2 inch max.
Test Point
25 10 pF
VCC
Figure 5. TVAL (max) Falling Edge Test Load
Pin 1/2 inch max.
Test Point
1k
10 pF
1k
VCC
Figure 6. TVAL (minimum.) Test Load
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82541 Family of Gigabit Ethernet Controllers
Pin 1/2 inch max.
Test Point
50 pF
NOTE: 50 pF load used for maximum times. Minimum times are specified with 0 pF load.
Figure 7. TVAL Test Load (PCI 5 V Signaling Environment)
4.5.2
Link Interface Timing
Table 21. Rise and Fall Times
Symbol TR TF TR TF Parameter Clock rise time Clock fall time Data rise time Data fall time Condition 0.8 V to 2.0 V 2.0 V to 0.8 V 0.8 V to 2.0 V 2.0 V to 0.8 V Min 0.7 0.7 0.7 0.7 Max Unit ns ns ns ns
2.0 V
0.8 V
TR
TF
Figure 8. Link Interface Rise/Fall Timing
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Datasheet
82541 Family of Gigabit Ethernet Controllers
4.5.3
EEPROM Interface
Table 22. Link Interface Clock Requirements
Symbol Parametera Microwire EE_SK pulse width TPW SPI EE_SK pulse width
a. The EEPROM clock is derived from a 125 MHz internal clock. TPERIOD x
Min
Typ TPERIOD x 64 32
Max
Unit ns ns
Table 23. Link Interface Clock Requirements
Symbol TDOS TDOH Parametera EE_DO setup time EE_DO hold time Min TCYC*2 0 Typ Max Unit ns ns
a. The EE_DO setup and hold time is a function of the PCI bus clock cycle time but is referenced to O_EE_SK.
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82541 Family of Gigabit Ethernet Controllers
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This page is intentionally left blank.
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Datasheet
82541 Family of Gigabit Ethernet Controllers
5.0
Package and Pinout Information
This section describes the 82541PI/GI/EI device physical characteristics. The pin number-to-signal mapping is indicated beginning with Table 14.
5.1
Package Information
The 82541PI/GI/EI device is a 196-lead plastic ball grid array (BGA) measuring 15 mm by 15mm. The package dimensions are detailed below. The nominal ball pitch is 1 mm.
Figure 11. 82541PI/GI/EI Mechanical Specifications
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82541 Family of Gigabit Ethernet Controllers
Detail Area
0.45 Solder Resist Opening
0.60 Metal Diameter
Figure 12. 196 PBGA Package Pad Detail As illustrated in Figure 12, the Ethernet controller package uses solder mask defined pads. The copper area is 0.60mm and the opening in the solder mask is 0.45mm. The nominal ball sphere diameter is 0.50mm.
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82541 Family of Gigabit Ethernet Controllers
5.2
Thermal Specifications
The 82541PI/GI/EI device is specified for operation when the ambient temperature (TA) is within the range of 0 C to 70 C. TC (case temperature) is calculated using the equation: TC = TA + P (JA - JC) TJ (junction temperature) is calculated using the equation: TJ = TA + P JA P (power consumption) is calculated by using the typical ICC, as indicated in Table 7 of Section 4.0, and nominal VCC. The preliminary thermal resistances are shown in Table 13.
Table 13. Thermal Characteristics
Preliminary Value at specified airflow (m/s) 0 JA JC Thermal resistance, junction-to-ambient Thermal resistance, junction-to-case 29 11.1 1 25.0 11.1 2 23.5 11.1 C/Watt C/Watt
Symbol
Parameter
Units
Thermal resistances are determined empirically with test devices mounted on standard thermal test boards. Real system designs may have different characteristics due to board thickness, arrangement of ground planes, and proximity of other components. The case temperature measurements should be used to assure that the 82541PI/GI/EI device is operating under recommended conditions.
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82541 Family of Gigabit Ethernet Controllers
5.3
Pinout Information
Table 14. PCI Address, Data and Control Signals
Signal PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] Pin N7 M7 P6 P5 N5 M5 P4 N4 P3 N3 N2 M1 M2 M3 L1 L2 Signal PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] Pin K1 E3 D1 D2 D3 C1 B1 B2 B4 A5 B5 B6 C6 C7 A8 B8 Signal CBE0# CBE1# CBE2# CBE3# PAR FRAME# IRDY# TRDY# STOP# DEVSEL# IDSEL VIO Pin M4 L3 F3 C4 J1 F2 F1 G3 H1 H3 A4 G2
Table 15. PCI Arbitration Signals
Signal REQ# GNT# Pin C3 J3
Table 16. Interrupt Signals
Signal INTA# Pin H2
Table 17. System Signals
Signal CLK M66EN Pin G1 C2 RST# CLKRUN# Signal Pin B9 C8
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Table 18. Error Reporting Signals
Signal SERR# Pin A2 Signal PERR# Pin J2
Table 19. Power Management Signals
Signal PME# LAN_PWRGD Pin A6 A9 Signal AUX_PWR Pin J12
Table 20. SMB Signals
Signal SMBCLK Pin A10 Signal SMBDATA Pin C9 Signal SMBALRT# Pin B10
Table 21. Serial EEPROM Interface Signals
Signal EE_SK EE_DO Pin M10 N10 Signal EE_DI EE_MODE Pin P10 J4 Signal EE_CS Pin P7
Table 22. Serial FLASH Interface Signals
Signal FLSH_SCK FLSH_SO/LAN_DISABLE# Pin N9 P9 Signal FLSH_SI Pin M11 Signal FLSH_CE# Pin M9
Table 23. LED Signals
Signal LED0 / LINKUP# LED1 / ACT# Pin A12 C11 Signal LED2 / LINK100# LED3 / LINK1000# Pin B11 B12
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82541 Family of Gigabit Ethernet Controllers
Table 24. Other Signals
Signal SDP0 SDP1 N14 P13 Pin SDP2 SDP3 Signal N13 M12 Pin
Table 25. IEEE Test Signals
Signal IEEE_TESTPin D14 Signal IEEE_TEST+ Pin B14
Table 26. PHY Signals
Signal MDI0MDI0+ MDI1MDI1+ C14 C13 E14 E13 Pin Signal MDI2MDI2+ MDI3MDI3+ F14 F13 H14 H13 Pin Signal XTAL1 XTAL2 K14 J14 Pin
Table 27. Test Interface Signals
Signal JTAG_TCK JTAG_TDI Pin L14 M13 Signal JTAG_TDO JTAG_TMS Pin M14 L12 Signal JTAG_TRST# TEST Pin L13 A13
Table 28. Digital Power Signals (Sheet 1 of 2)
Signal 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V A3 A7 A11 E1 K3 K4 K13 N6 N8 Pin 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Signal G5 G6 H5 H6 H7 H8 J10 J11 J5 Pin 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Signal J9 K10 K11 K5 K6 K7 K8 K9 L10 Pin
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Table 28. Digital Power Signals (Sheet 2 of 2) (Continued)
Signal 3.3V 3.3V P2 P12 Pin 1.2V 1.2V 1.2V Signal J6 J7 J8 Pin 1.2V 1.2V 1.2V Signal L4 L5 L9 Pin
Table 29. Analog Power Signals
Signal Analog_1.2V Analog_1.2V Analog_1.2V Analog_1.2V E11 E12 G13 H11 Pin Signal Analog 1.8V Analog_1.8V PLL_1.2V PLL_1.2V Pin D11 G12 G4 H4 Signal CLKR_1.8V XTAL_1.8V D12 J13 Pin
Table 30. Grounds and No Connect Signals
Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin B3 B7 C10 D5 D6 D7 D8 E10 E2 E5 E6 E7 E8 E9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Signal Pin F10 F4 F5 F6 F7 F8 F9 G10 G7 G8 G9 H10 H9 K2 Signal VSS VSS VSS VSS VSS VSS AVSS AVSS AVSS AVSS AVSS AVSS NC NC Pin L11 L6 M6 N1 N12 P8 C12 D13 F11 G11 G14 K12 A1 A14 Signal NC NC NC NC NC NC RSVD_NC RSVD_NC RSVD_NC RSVD_NC RSVD_NC RSVD_VSS RSVD_VSS Pin D10 D9 H12 L8 P1 P14 C5 L7 M8 N11 F12 D4 E4
Table 31. Voltage Regulation Control Signals
Signal CTRL_18 Pin B13 Signal CTRL_12 Pin P11
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82541 Family of Gigabit Ethernet Controllers
Table 32. Signal Names in Pin Order (Sheet 1 of 6)
Signal Name NC SERR# 3.3V IDSEL PCI_AD[25] PME# 3.3V PCI_AD[30] LAN_PWRGD SMBCLK 3.3V LED0 / LINKUP# TEST NC PCI_AD[22] PCI_AD[23] VSS PCI_AD[24] PCI_AD[26] PCI_AD[27] VSS PCI_AD[31] RST# SMBALRT# LED2 / LINK100# LED3 / LINK1000# CTRL_18 IEEE_TEST+ PCI_AD[21] M66EN REQ# CBE3# RSVD_NC Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5
38
Datasheet
82541 Family of Gigabit Ethernet Controllers
Table 32. Signal Names in Pin Order (Sheet 2 of 6) (Continued)
PCI_AD[28] PCI_AD[29] CLK_RUN# SMBDATA VSS LED1 / ACT# AVSS MDI0+ MDI0PCI_AD[18] PCI_AD[19] PCI_AD[20] RSVD_VSS VSS VSS VSS VSS NC NC Analog_1.8V CLKR_1.8V AVSS IEEE_TEST3.3V VSS PCI_AD[17] RSVD_VSS VSS VSS VSS VSS VSS VSS Analog_1.2V Analog_1.2V MDI1+ C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13
Datasheet
39
82541 Family of Gigabit Ethernet Controllers
Table 32. Signal Names in Pin Order (Sheet 3 of 6) (Continued)
MDI1IRDY# FRAME# CBE2# VSS VSS VSS VSS VSS VSS VSS AVSS RSVD_NC MDI2+ MDI2CLK VIO TRDY# PLL_1.2V 1.2V 1.2V VSS VSS VSS VSS AVSS Analog_1.8V Analog_1.2V AVSS STOP# INTA# DEVSEL# PLL_1.2V 1.2V 1.2V 1.2V E14 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7
40
Datasheet
82541 Family of Gigabit Ethernet Controllers
Table 32. Signal Names in Pin Order (Sheet 4 of 6) (Continued)
1.2V VSS VSS Analog_1.2V NC MDI3+ MDI3PAR PERR# GNT# EE_MODE 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V AUX_PWR XTAL_1.8V XTAL2 PCI_AD[16] VSS 3.3V 3.3V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V AVSS 3.3V XTAL1 PCI_AD[14] H8 H9 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1
Datasheet
41
82541 Family of Gigabit Ethernet Controllers
Table 32. Signal Names in Pin Order (Sheet 5 of 6) (Continued)
PCI_AD[15] CBE1# 1.2V 1.2V VSS RSVD_NC NC 1.2V 1.2V VSS JTAG_TMS JTAG_TRST# JTAG_TCK PCI_AD[11] PCI_AD[12] PCI_AD[13] CBE0# PCI_AD[5] VSS PCI_AD[1] RSVD_NC FLSH_CE_N# EE_SK FLSH_SI SDP3 JTAG_TDI JTAG_TDO VSS PCI_AD[10] PCI_AD[9] PCI_AD[7] PCI_AD[4] 3.3V PCI_AD[0] 3.3V FLSH_SCK L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9
42
Datasheet
82541 Family of Gigabit Ethernet Controllers
Table 32. Signal Names in Pin Order (Sheet 6 of 6) (Continued)
EE_DO RSVD_NC VSS SDP2 SDP0 NC 3.3V PCI_AD[8] PCI_AD[6] PCI_AD[3] PCI_AD[2] EE_CS VSS FLSH_SO EE_DI CTRL_12 3.3V SDP1 NC N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14
Datasheet
43
82541 Family of Gigabit Ethernet Controllers
5.4
A 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Visual Pin Assignments
B
IEEE TEST+
C
D
E
F
G
H
J
K
L
M
N
P 14 13 12 11 10 9 8 7 6 5 4 3 2 1
NC
MDI-
[0] IEEE TEST- MDI-
[1] MDI-
[2]
AVSS
MDI-
[3]
XTAL2
XTAL1
JTAG TCK JTAG TDO
SDP [0]
NC
TEST
CTRL18
MDI+ [0]
AVSS
MDI+ [1]
MDI+ [2]
Analog 1.2V
MDI+ [3] XTAL 1.8V
3.3V
JTAG TRST#
JTAG TDI
SDP [2]
SDP [1]
LINK UP#
LINK 1000#
AVSS
CLKR 1.8V
Analog 1.2V
RSVD_NC
Analog 1.8V
NC
AUX PWR
AVSS
JTAG TMS
SDP [3]
VSS
3.3V
3.3V
LINK 100#
ACT#
Analog 1.8V
Analog 1.2V
AVSS
AVSS
Analog 1.2V
1.2V
1.2V
VSS
FLSH SI RSVD NC
CTRL12
RSVD VCC
RSVD VCC
VSS
NC
VSS
VSS
VSS
VSS
1.2V
1.2V
1.2V
EE_ SK
EE_ DO
EE_ DI
LAN PWRGD
RST#
SMB DAT
NC
VSS
VSS
VSS
VSS
1.2V
1.2V
1.2V
FLSH CE_N
FLSH SCK FLSH
SO
AD30
AD31
CLK RUN#
VSS
VSS
VSS
VSS
1.2V
1.2V
1.2V
NC
RSVD NC
3.3V
VSS
3.3V
VSS
AD29
VSS
VSS
VSS
VSS
1.2V
1.2V
1.2V
RSVD NC
AD1
AD0
EE_ CS
PME#
AD27
AD28
VSS
VSS
VSS
1.2V
1.2V
1.2V
1.2V
VSS
VSS
3.3V
AD2
AD25
AD26
RSVD NC
VSS
VSS
VSS
1.2V
1.2V
1.2V
1.2V
1.2V
AD5
AD4
AD3
IDSEL
AD24
CBE# [3]
RSVD VSS
RSVD VSS
VSS
PLL 1.2V PLL 1.2V EE MODE
3.3V
1.2V
CBE# [0]
AD7
AD6
3.3V
VSS
REQ#
AD20
AD17
CBE# [2]
TRDY#
DEV SEL#
GNT#
3.3V
CBE# [1]
AD13
AD9
AD8
SERR#
AD23
M66EN
AD19
VSS
FRAME#
VIO
INTA#
PERR#
VSS
AD15
AD12
AD10
3.3V
NC
AD22
AD21
AD18
3.3V
IRDY#
CLK
STOP#
PAR
AD16
AD14
AD11
VSS
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 13. Visual Pin Assignments
44
Datasheet

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